1. Field of the Invention
This invention relates generally to digital logic circuits and more particularly, to a MOSFET latching circuit.
2. Description of the Prior Art
Latching circuits are commonly used within larger digital circuits for monitoring the status of an input signal. The latching circuit is initialized to a first logic state while the input signal is in the passive state. At a later time, the input signal may switch from the passive to an active state, at which time the latching circuit switches to a logic state opposite to that from which it was initialized. The latching circuit now "remembers" that the input signal was in its active state even if the input signal subsequently returns to the passive state.
Often a latching circuit consists of a first logic circuit and a second logic circuit. The first logic circuit has two inputs, a first for receiving the input signal to be monitored, and the second for receiving a feedback signal. The output of the first logic circuit is typically coupled to the input of the second logic circuit, and the output of the second logic circuit typically provides the feedback signal.
In a particular application, it was desired to have active and passive states of the input signal corresponding to voltage signals having magnitudes of 0 volts and +5 volts, respectively. The first logic circuit can be a series connected structure (e.g., a NAND gate) such that the occurrence of the active state of the input signal (0 volts) will block current from flowing in the series connected structure. Also in this particular circuit application, it was desired to provide an output signal having a voltage of magnitude 0 volts immediately following the initialization of the latching circuit, and switching to a magnitude of +5 volts when the active state of the input signal is detected and latched. A further constraint on this circuit application is that the output of the latching circuit must be capable of transmitting the output signal to a highly capacitive data bus which is precharged to a positive voltage. Thus it is important for the latching circuit to provide a low impedance path to ground potential to provide efficient discharging of the data bus.
Prior art circuitry suggests several alternatives for complying with the constraints imposed upon this circuit application. A first alternative is the addition of a third logic circuit, for example an inverter circuit, having an input coupled to the output of the second logic circuit and an output suitable for driving a data bus. However the additional components required to form this third logic circuit require additional chip area if the latching circuit is fabricated as a monolithic integrated circuit. A second alternative suggested by the prior art is to employ relatively large series connected devices within the first logic circuit such that the total series impedance of first and second series connected devices is small enough to efficiently discharge the data bus. However the need for larger devices again increases the chip area consumed by the latching circuit if the latching circuit is fabricated as an integrated circuit. Increased chip area necessarily results in a smaller number of good integrated circuits per processed wafer and therefore higher cost per integrated circuit. Thus it will be appreciated that a latching circuit which fulfills the aforementioned circuit design constraints without increasing the required chip area to fabricate the latching circuit is a significant improvement over the prior art.